The demand for small sized portable communication devices such as cellular telephones, handheld devices, memory cards, smart cards, etc. has lead to a need to develop smaller integrated circuit packages (although use of such small size IC packages are also applicable to larger devices like notebooks, laptops, desktops, game consoles, DTVs, workstations, servers and other computing devices). However, as these communication devices shrink in size, integrated circuit packages must also be reduced both in thickness and in footprint. Reducing die thickness is an important consideration in reducing package dimensions (such as thickness and footprint). To accomplish this, some die stacking solutions are currently being implemented. Die stacking refers to a process of mounting multiple chips on top of each other within a single integrated circuit/semiconductor package. Die stacking, also referred to as “chip stacking”, significantly increases the amount of silicon chip area that can be housed within a single package of a given footprint to, thus, conserve precious real estate on a printed circuit board and simplify a board assembly process.
Current solutions that employ die stacking are known to use either a stack wire bond device or a hybrid package. Stack wire bond can be used in a package that combines several dies vertically in a chip scale package and electrically interconnects them to form a single device. Stacked multichip packaging methodologies have recently become a means in helping system designers restrain the size, weight, power consumption, and cost of small, portable, and wireless consumer devices. However, for some complex designs, there can be difficulties in routing numerous wire bonds when the dimensions of the package are constrained.
One method to try to overcome these difficulties involves die stacking in hybrid packages. A hybrid package refers to a special carrier of hybrid microcircuits and components interconnected as one unit. It can be considered a component of an electronic subsystem. The hybrid package may consist of a single construction or be made up of sub-modules. Each module usually contains a compartment to house the hermetically packaged hybrids and discrete passive component parts such as transformers, resistors, etc. However, some of the challenges facing hybrid packages are that as the die sizes are continually being pushed down, the input/output requirements are continually getting bigger.
Thus, although wire bond dies and flip chip dies have been employed in some stack die small packaging applications, the inefficiencies in current available arrangements have limited the amount of I/O counts that may be derived from such packaging. A flip-chip is a semiconductor device typically in the form of a die mounted directly onto a substrate (e.g., a carrier) in a “face-down” manner. An electrical connection is achieved through conductive bumps attached to the surface of the die. During mounting, the chip is flipped on the substrate (hence the name “flip-chip”), with bumps being positioned on respective target locations. In one method, the chip is placed face down so the solder bumps on the chip are aligned and contact bond pads on the package.
The device is reflowed (heated) so that the solder bumps and bond pads form metallurgical bonds. Flip-chips are typically smaller than conventional chips because they do not require wirebonds.
Stacked dies may be interconnected using wirebonding alone, or by a combination of wirebonding and flipchip assembly. The use of wirebonding as the exclusive means of interconnection is somewhat restrictive, since the number of stacked dies that may be wirebonded may be very limited.
Moreover, conventional redistribution layers (RDLs) are known in art. Redistribution layers are known to facilitate the redistribution (or relocation) of electrical signals, power and ground information, from one location to another location within an integrated circuit. Such conventional redistribution layers are known to have pads that can be suitable for only solder pad connections. Other conventional redistribution layers are known to have pads that can be suitable for only wire bond connections. Perhaps due to metallization challenges, none of current redistribution layer structures are known to include both solder pad connections and wire bond connections on the same substrate. Such limitations are of concern since advances in chip scale packaging, wafer-level packaging, 3-D packaging, and system-in-package often require redistributed bond pads. Thus, conventional RDL structures need to use multiple substrates in order to achieve desired solder pad and wire bond connections. Having multiple layered substrates in the same package can be expensive, and can defeat a goal of shrinking the sizes of communication devices.
Thus, such conventional techniques of integrating more peripheral devices onto a single monolithic chip to achieve improved performance but being restricted by inefficient ways of interconnecting these devices has resulted in higher power consumption in such devices. It is therefore desirable to provide, among other things, an improved integrated circuit.